Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
FIG. 1 depicts a reference clock doubler circuit 100 and FIG. 2 shows waveforms of the reference clock doubler circuit 100. A buffer 102 outputs a full-swing clock, C1. A delay element 104 delays the full-swing clock C1 and outputs a delayed full-swing clock C2b. A logic element 106 (e.g., XOR gate) outputs a doubled reference clock C2x. The rising edges of the doubled reference clock C2x comes from the rising and falling edges of the C1 clock. The edges of the doubled reference clock C2x come from the rising and falling edges of the delayed full-swing clock C2b. The non-50% duty cycle in clock signal C1 causes a mismatch between the even clock period, Tref,even, and odd clock period, Tref,odd, in the doubled reference clock C2x. For example, the mismatch causes high-reference spur. Additionally, a higher average “on time” is forced for charge pump in a phase lock loop (PLL) using the doubled reference clock signal and also for time-to-digital converters (TDCs) for digital PLLs, which increases the phase noise due to the charge pump or TDC thermal and flicker noise.
FIG. 3 depicts a PLL 109 illustrating the reference doubler problem. A phase frequency detector (PFD) 110 receives a reference clock clkref (e.g., doubled reference clock C2x) and a feedback clock clkfb. Phase frequency detector 110 outputs an up and down signal that represents the difference in phase between the two input signals. An up and down signal is output to a charge pump 112. Charge pump 112 charges capacitors C1 and C2 of a loop filter when an up switch 506-1 is dosed and dissipates charge when a down switch 506-2 is closed. VCO 114 receives a tuning voltage from the loop filter and generates an oscillating signal with a frequency controlled by tuning voltage. A divider 116 divides the output of VCO 114 to generate the feedback signal clkfb.
At 117, a summary of the waveforms for signals received and output at PFD 110 is shown. At 118, reference clock clkref is shown; at 120, feedback clock clkfb is shown; at 122, an up signal is shown; and at 124, a down signal is shown. The even and odd cycles of reference clock clkref are not the same length. The up signal is generated by PFD 110 when a rising edge of reference clock clkref is before a rising edge of the feedback clock clkfb. The down signal is generated when the rising edge of the reference clock clkref is after a rising edge of the feedback clock clkfb. The up and down signals alternate every even and odd dock period.
The up and down signals deliver charge to capacitors C1 and C2 that cancel each other. However, uncorrelated noise may be received and increases in-band noise. For example, at 128, VCO 114 up-converts the noise received into reference spurs. One solution to correct the mismatch is to add digital and analog tuning to adjust the duty cycle of reference clock clkref. However, the analog tuning increases the noise. Also, digital tuning cannot track temperature variation without introducing large glitches to the output clock.